Semiconductor Economics
Cost structures, Moore's Law economics, and market dynamics
The Cost Structure of a Chip
The Cost Structure of a Chip
Understanding chip economics requires understanding where the money goes:
| Cost Component | Percentage | Notes |
|---|---|---|
| Wafer fabrication | 30–40% | Equipment depreciation, materials, labor, utilities |
| Design (R&D) | 20–30% | Amortized over units sold; higher for low-volume chips |
| Packaging & test | 10–20% | Rising due to advanced packaging |
| IP licensing | 5–15% | ARM royalties, other licensed IP blocks |
| Sales & marketing | 5–10% | Distribution, customer support |
Key Concept: The NRE Wall
Non-Recurring Engineering (NRE) costs — the one-time design costs — have skyrocketed. Designing a chip at the 3nm node costs $500M–$1B+. This means only very high-volume chips (smartphones, GPUs) can justify leading-edge nodes.
Moore's Law Economics
Moore's Law Economics
Moore's Law (1965) observed that the number of transistors on a chip doubles roughly every two years. The economic consequence was that the cost per transistor dropped with each new generation — making electronics progressively cheaper.
However, this economic scaling has slowed:
- Moving from 7nm to 5nm to 3nm provides fewer transistors-per-dollar improvements
- EUV lithography and multi-patterning dramatically increase fab costs
- Advanced packaging adds cost but enables new system architectures
The industry response has been:
- Chiplets: Use older, cheaper nodes for less critical functions
- Heterogeneous integration: Combine different technologies in one package
- Domain-specific accelerators: Custom chips (like AI accelerators) that deliver more performance per transistor
Analogy: The Skyscraper Problem
Building a 10-story building costs less per floor than building a 100-story building. Similarly, each new semiconductor node delivers diminishing cost-per-transistor improvements while requiring exponentially more investment. The solution? Build several specialized medium-rise buildings (chiplets) instead of one mega-tower.
Knowledge Check
Knowledge Check
1 / 2How much does it cost to design a chip at the 3nm node?