Inside a Chip
What's actually on a silicon die — layers, transistors, and basic structure
Layers of a Modern Chip
Layers of a Modern Chip
A modern processor isn't just a flat piece of silicon — it's a 3D structure with dozens of layers built on top of each other. From bottom to top:
- Silicon substrate: The wafer itself — the foundation everything is built on.
- Transistor layer (FEOL): Billions of transistors are formed in and on the silicon surface. This is the "front-end-of-line" (FEOL).
- Contact layer: Tiny plugs connect transistors to the wiring above.
- Metal interconnects (BEOL): 10-15 layers of copper wiring connect transistors to each other. Lower layers are thin and dense (local connections), upper layers are thick (power distribution and long-distance signals).
- Passivation & pads: A protective top layer with exposed metal pads for bonding to the package.
Analogy: A Skyscraper
Think of a chip as a city skyscraper. The foundation (silicon) holds everything up. The ground floor has all the workers (transistors doing the computation). Above them are floors of hallways and corridors (metal layers) connecting offices. The higher floors have wider hallways for main traffic arteries.
Transistor Scale
Transistor Scale
Modern chips contain a staggering number of transistors:
| Chip | Year | Transistors | Process Node |
|---|---|---|---|
| Intel 4004 | 1971 | 2,300 | 10 µm |
| Intel Pentium | 1993 | 3.1 million | 800 nm |
| Apple M1 | 2020 | 16 billion | 5 nm |
| Apple M4 Ultra | 2025 | ~100 billion | 3 nm |
Each transistor is incredibly small. At the 3nm node, transistor features are just a few nanometers wide — about 20 silicon atoms across. A human hair is roughly 80,000 nm wide.
Key Concept: Die Size
A single chip (die) typically ranges from 50 mm² to 800 mm² in area. A 300mm wafer can yield hundreds of small dies or dozens of large ones. Larger dies = more transistors but lower yield and higher cost.
Knowledge Check
Knowledge Check
1 / 2What does FEOL stand for in chip manufacturing?