Epitaxy Reactor Design
Epitaxy Reactor Design
Epitaxy requires the highest cleanliness and temperature control of any deposition process:
- Single-wafer reactors: Dominant for advanced logic. The wafer sits on a rotating susceptor in a cold-wall chamber. Lamp heating provides rapid temperature ramping (50°C/s) to process temperatures of 500–1100°C.
- Gas system: Ultra-pure precursors (SiH₄, SiH₂Cl₂, GeH₄) with ppb-level purity requirements. Mass flow controllers provide precise gas composition control for SiGe alloy composition.
- In-situ monitoring: Real-time measurements during growth:
- Pyrometry for wafer temperature
- Reflectometry for film thickness and growth rate
- Residual gas analyzers for chamber cleanliness
- Selective epi: HCl is added to the gas mix to etch deposited material on non-silicon surfaces while allowing growth on exposed silicon only.
Key Concept: Pre-epi Clean
Even a single monolayer of oxide or carbon on the silicon surface will prevent epitaxial growth. Reactors include an in-situ hydrogen bake (800–1100°C) to remove native oxide before growth. This clean step is as critical as the deposition itself.
Selective Epitaxy in Modern Transistors
Selective Epitaxy in Modern Transistors
Selective epitaxial growth (SEG) is one of the highest-leverage modules in advanced CMOS. The trick is to add a small amount of HCl to the SiH₂Cl₂/GeH₄ chemistry so that any Si or SiGe that nucleates on SiO₂ or SiN is immediately etched, while growth on exposed Si surfaces proceeds.
Where SEG appears in the FinFET / nanosheet flow:
- Raised source/drain (RSD): Faceted SiGe:B (PMOS) or Si:P/Si:As (NMOS) is grown above the fin to add silicon volume — lowers spreading resistance and provides strain.
- Embedded SiGe (eSiGe) for PMOS: Source/drain pockets are recessed and refilled with SiGe ~25–35% Ge. The larger Ge lattice puts the channel under uniaxial compression, boosting hole mobility 50–100%.
- Embedded Si:C for NMOS: Substitutional carbon (~1%) puts the channel under tension, boosting electron mobility ~10–15%.
- Nanosheet inner-spacer step: The sacrificial SiGe between Si nanosheets is selectively etched; epi later refills the cavity with replacement Si.
| Vendor | Epi platform | Notes |
|---|---|---|
| Applied Materials | Centura RP Epi | Industry workhorse for Si/SiGe epi at 7nm and below |
| ASM International | Intrepid XP / Epsilon | Strong in selective epi and SiGe alloy uniformity |
| Tokyo Electron | Triase+ Epi | Logic and DRAM epi |
Key Concept: Loading Effect
Selective epi growth rate depends on the local ratio of exposed Si to dielectric — a phenomenon called the loading effect. Dense arrays of small openings grow slower than isolated openings. Process engineers manage this with HCl flow tuning and lithography dummy-fill rules.
Knowledge Check
Knowledge Check
1 / 2Why is an in-situ hydrogen bake performed before epitaxial growth?