Etch Chamber Configurations
Etch Chamber Configurations
Plasma etch chambers come in two main configurations, each suited to different applications:
- CCP (Capacitively Coupled Plasma): Two parallel plate electrodes create the plasma. The wafer sits on the bottom electrode (cathode). RF power applied to the electrodes both generates the plasma and accelerates ions toward the wafer. CCP systems offer moderate plasma density and good ion energy control. Used for dielectric etching.
- ICP (Inductively Coupled Plasma): A coil (usually on top of the chamber) generates a high-density plasma via inductive coupling. A separate RF bias on the wafer chuck controls ion energy independently. ICP provides 10–100× higher plasma density than CCP, enabling faster etch rates and better profile control. Used for conductor and high-aspect-ratio etching.
Modern etch tools often combine both: TCP (Transformer Coupled Plasma) configurations use a planar coil above the chamber with independent source and bias power for maximum flexibility.
Key Concept: Independent Source/Bias Control
Decoupling plasma generation (source power → ion density) from ion acceleration (bias power → ion energy) is critical. It allows engineers to independently tune the chemical and physical components of the etch — more chemical for selectivity, more physical for anisotropy.
Major Etch Tools and Vendors
Major Etch Tools and Vendors
Three vendors share the etch market for advanced logic and memory:
| Vendor | Platform | Configuration | Sweet spot |
|---|---|---|---|
| Lam Research | Kiyo (conductor), Flex (dielectric), Sense.i | TCP / ICP + dual-frequency bias | Conductor etch, 3D NAND HARC |
| Applied Materials | Centura Sym3 / Producer | CCP w/ dual-frequency & multi-zone | Dielectric etch, advanced logic |
| Tokyo Electron | Tactras (CCP), Telius (ICP) | CCP and ICP variants | DRAM, logic, broad coverage |
Pulsed plasma — a recent step change
Modern tools modulate source and/or bias RF on a kHz timescale. Pulsing gives:
- Lower electron temperature on average — less charging damage on thin dielectrics
- Better ion energy control — narrower ion-energy distributions, key for atomic-scale etch
- Atomic Layer Etch (ALE) — alternating self-limiting chemistry and low-energy ion bombardment to remove one atomic layer per cycle, mirroring ALD
Key Concept: HARC Etch
3D NAND stacks 100+ layers and requires High Aspect Ratio Contact (HARC) etches with aspect ratios above 60:1. The CCP/ICP balance, sidewall passivation chemistry, and stage temperature (often cryogenic, ~−80 °C) are all pushed to extremes to keep the hole straight and the bottom open.
Knowledge Check
Knowledge Check
1 / 2What advantage does ICP have over CCP for plasma etching?