Copper Damascene Process

Dual damascene, electroplating, and CMP — how copper wires are made

The Damascene Process

Copper can't be plasma-etched like aluminum (copper halides aren't volatile). Instead, the industry uses the damascene process — named after the ancient art of inlaying metal into grooves:

1. Dielectric deposition: Deposit and planarize the insulating layer (low-k SiOCH or SiO₂)
2. Pattern & etch trenches: Lithography and etch to create trenches (for wires) and vias (for vertical connections)
3. Barrier/liner deposition: PVD TaN/Ta to prevent copper diffusion into the dielectric
4. Copper seed layer: PVD thin copper film as the electrode for electroplating
5. Copper electroplating: Fill trenches and vias with copper from a plating bath
6. CMP: Chemical-mechanical polishing removes excess copper, leaving copper only in the trenches

In dual damascene, the trench and via are etched and filled simultaneously, reducing the number of process steps.

Key Concept: Why Copper Replaced Aluminum

Copper has 40% lower resistivity than aluminum (1.7 vs 2.8 µΩ·cm), enabling faster signal propagation and lower power consumption. The switch from Al to Cu at the 130nm node was a major industry milestone.

Electroplating and CMP

Electroplating and CMP — The Two Steps That Made Damascene Possible

Two enabling unit processes turned the damascene idea into a manufacturable flow:

1. Electrochemical Deposition (ECD) — the bottom-up fill

Pure copper PVD would close the top of a high-aspect-ratio trench before filling the bottom, leaving a void. Modern Cu ECD baths add three families of organic additives that bias growth bottom-up:

Suppressor (e.g., PEG with Cl⁻): adsorbs everywhere, slows plating on the field
Accelerator (SPS / MPS): preferentially accumulates at trench bottoms, speeds plating locally
Leveler (Janus Green B): diffusion-limited; adsorbs on protrusions to smooth the surface

The combined effect — "superfilling" — gives void-free fill in trenches with aspect ratio > 5:1.

2. Chemical-Mechanical Polishing (CMP)

ECD overplates copper across the entire wafer. CMP removes the overburden plus the barrier on the field, stopping flush with the dielectric and leaving copper only in the trenches.

Slurry: nano-alumina or silica abrasives suspended in oxidiser (H₂O₂) + complexing agents
Pad: porous polyurethane, rotating at 30–100 rpm under 2–7 psi down-force
Endpoint: motor-torque or eddy-current sensor detects the transition from Cu to barrier to dielectric

Key Concept: Dishing and Erosion

Two CMP defects haunt damascene: dishing (the centre of wide Cu lines polishes faster than the edges, giving a concave wire) and erosion (dense arrays of small lines polish faster than the surrounding dielectric). Both eat resistance budget and force layout-level dummy-fill rules to keep pattern density uniform.

Why Interconnects Matter

Barrier & Liner Layers

Knowledge Check

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Why is the damascene process used for copper instead of etching?

Copper halides aren't volatile, so copper can't be plasma-etched effectivelyDamascene is cheaper than etchingCopper is too hard to etchEtching would damage the transistors