Why Interconnects Matter

RC delay, signal speed, and power distribution challenges

The Interconnect Challenge

As transistors have shrunk, interconnects have become the performance bottleneck. While transistor switching speeds improve with scaling, interconnect delays increase because:

Higher resistance (R): Thinner, narrower wires have more resistance
Higher capacitance (C): Wires packed closer together have more parasitic capacitance
RC delay: Signal propagation delay = R × C, which increases as features shrink

At the 90nm node, interconnect delay surpassed transistor delay as the dominant factor. Today, interconnect optimization is as critical as transistor engineering.

Analogy: Highway Traffic

Imagine making cars (transistors) faster, but also making roads (interconnects) narrower and more crowded. Eventually, traffic congestion on the roads — not the cars' top speed — determines how fast you can get anywhere. That's the interconnect problem.

The Metal Layer Hierarchy

Modern chips use 10–15+ metal layers, organized in a hierarchy:

Local interconnects (M1–M3): Very thin and narrow. Connect nearby transistors and gates. Tightest pitch (~20–28 nm at advanced nodes).
Intermediate layers (M4–M8): Moderate dimensions. Route signals between functional blocks.
Global/semi-global (M9+): Thick, wide wires for power distribution (VDD/VSS) and long-distance clock/signal routes.

The total length of metal wiring in a single chip can exceed 100 kilometers — packed into a die smaller than your fingernail.

Annealing & Activation

Copper Damascene Process

Knowledge Check

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At which technology node did interconnect delay surpass transistor delay?

~90 nm~3 nm~500 nm~14 nm